Method for producing power semiconductor device with heat dissipating capability

ABSTRACT

A method for producing a power semiconductor device with heat dissipating capability includes epitaxially growing a GaN-based buffer layer on a first surface of a sapphire substrate, epitaxially growing a Ga2O3 semiconductor layer on the GaN-based buffer layer, forming a source and a drain, a gate dielectric layer, a first gate, an insulator layer, and a metal adhesive layer in sequence, removing part of the metal adhesive layer, the insulator layer, and the gate dielectric layer to expose one of the source and the drain, forming a heat sink which covers the metal adhesive layer, the insulator layer, the gate dielectric layer, and the one of the source and the drain, and conducting a laser lift-off process through a second surface of the sapphire substrate to remove the sapphire substrate and the GaN-based buffer layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese Invention PatentApplication No. 110140786, filed on Nov. 2, 2021.

FIELD

The disclosure relates to a power semiconductor device, moreparticularly to a method for producing a power semiconductor device withheat dissipating capability.

BACKGROUND

The first-generation semiconductor (the material of which is silicon(Si)) has an energy gap of 1.17 eV, making it suitable for powersemiconductor devices. With the evolution of the integrated circuitmanufacturing process, semiconductor devices have become lighter,thinner, shorter and smaller. The second-generation semiconductor (thematerial of which may be gallium arsenide (GaAs) and indium phosphide(InP)) and the third-generation semiconductor (the material of which maybe silicon carbide (SiC) and gallium nitride (GaN)) have also beendeveloped one after another.

Recently, the fourth-generation semiconductor (the material of which isgallium oxide (Ga₂O₃)) has an energy gap up to 4.9 eV and has receivedincreased interest from power semiconductor device industries. AlthoughGa₂O₃ is suitable to be applied to power semiconductor devices, thethermal conductivity (κ) of Ga₂O₃ is low, such that the powersemiconductor devices made thereof generate high heat during operation.Therefore, the power semiconductor devices made of Ga₂O₃ have severeheat dissipation problems.

At present, several techniques are applied to improve the heatdissipation of the power semiconductor devices made of Ga₂O₃. Asreported in Zhou, H. et al. (2017), ACS Omega, 2:7723-7729, Zhou, H. etal. have disclosed that the self-heating effect is a severe issue forhigh-power semiconductor devices, which degrades the electron mobilityand saturation velocity, and which also affects the device reliability.Zhou, H. et al. have further demonstrated that by utilizing a morethermally conductive sapphire substrate rather than a SiO₂/Si substrate,the temperature rise above room temperature of β-Ga₂O₃ on the insulatorfield-effect transistor can be reduced by a factor of 3 and thereby theself-heating effect is significantly reduced.

FIG. 1 is a schematic diagram illustrating the method disclosed by Zhou,H. et al. First, β-Ga₂O₃ nanomembranes are mechanically exfoliated froma Sn-doped ( 2 01) β-Ga₂O₃ bulk substrate's edge cleavage through ascotch tape method (not shown in FIG. 1 ). Next, referring to FIG. 1 ,the β-Ga₂O₃ nanomembranes are respectively transferred to a SiO₂/p⁺⁺ Sisubstrate 111 and a sapphire substrate 121 that are cleaned with acetonefor 24 hour prior to the transfer, so as to obtain corresponding β-Ga₂O₃2D flakes 112, 122. Thereafter, a corresponding one of Ti/Al/Au sources113, 123, a corresponding one of Ti/Al/Au drains 114, 124, acorresponding one of Al₂O₃ gate dielectric layers 115, 125, and acorresponding one of Ni/Au gate electrodes 116, 126 are formed on eachof the β-Ga₂O₃ 2D flakes 112, 122 using electron-beam lithography (EBL),photoresist stripping, and thin film deposition techniques in sequence,thereby obtaining a first β-Ga₂O₃ thin-film transistor 11 and a secondβ-Ga₂O₃ thin-film transistor 12. Both thermoreflectance characterizationand simulation verify that the thermal resistance on the second β-Ga₂O₃thin-film transistor 12 having the sapphire substrate 121 is less than ⅓of that on the first β-Ga₂O₃ thin-film transistor 11 having the SiO₂/p⁺⁺Si substrate 111.

Using the sapphire substrate 121 as the substrate of the second β-Ga₂O₃thin-film transistor 12 might solve the problem arising from theself-heating effect of the power semiconductor device. However, thethermal conductivity (κ) of sapphire is only about 40 W/m·K, so sapphirecannot effectively solve the problem of heat dissipation.

SUMMARY

Accordingly, the present disclosure provides a method for producing apower semiconductor device with heat dissipating capability, which canalleviate at least one of the drawbacks of the prior art, and whichincludes:

-   -   (a) epitaxially growing a GaN-based buffer layer having a        hexagonal crystal structure on a first surface of a sapphire        substrate;    -   (b) epitaxially growing a Ga₂O₃ semiconductor layer having a        monoclinic crystal structure on the GaN-based buffer layer;    -   (c) forming a source region and a drain region on two opposite        sides of the Ga₂O₃ semiconductor layer;    -   (d) forming a source and a drain that are respectively connected        to the source and drain regions of the Ga₂O₃ semiconductor        layer;    -   (e) forming a gate dielectric layer covering the Ga₂O₃        semiconductor layer, the source, and the drain;    -   (f) forming a first gate on the gate dielectric layer;    -   (g) forming an insulator layer on the first gate;    -   (h) forming a metal adhesive layer on the insulator layer;    -   (i) removing part of the metal adhesive layer, the insulator        layer, and the gate dielectric layer to expose one of the source        and the drain;    -   (j) conducting an electroforming process to form a heat sink        which covers the metal adhesive layer, the insulator layer, the        gate dielectric layer, and the one of the source and drain; and    -   (k) conducting a laser lift-off process through a second surface        of the sapphire substrate opposite to the first surface of the        sapphire substrate to remove the sapphire substrate and the        GaN-based buffer layer, so as to expose surfaces of the Ga₂O₃        semiconductor layer, the source, and the drain that are opposite        to the gate dielectric layer.

The present disclosure provides another method for producing a powersemiconductor device with heat dissipating capability, which canalleviate at least one of the drawbacks of the prior art, and whichincludes:

-   -   (a) epitaxially growing a GaN-based buffer layer having a        hexagonal crystal structure on a first surface of a sapphire        substrate;    -   (b) epitaxially growing a Ga₂O₃ semiconductor layer having a        monoclinic crystal structure on the GaN-based buffer layer;    -   (c′) forming a metal adhesive layer on the Ga₂O₃ semiconductor        layer;    -   (d′) conducting a wafer bonding process to form a heat sink on        the metal adhesive layer; and    -   (e′) conducting a laser lift-off process through a second        surface of the sapphire substrate opposite to the first surface        of the sapphire substrate to remove the sapphire substrate and        the GaN-based buffer layer, so as to expose a surface of the        Ga₂O₃ semiconductor layer opposite to the metal adhesive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the disclosure will become apparent inthe following detailed description of the embodiments with reference tothe accompanying drawings, of which:

FIG. 1 is a schematic sectional view illustrating two β-Ga₂O₃ thin-filmtransistors disclosed in Zhou, H. et al. (2017), supra;

FIG. 2 is a schematic sectional view illustrating steps (a) to (c) of afirst embodiment of a method for producing a power semiconductor devicewith heat dissipating capability according to the present disclosure;

FIG. 3 is a schematic sectional view illustrating steps (d) to (e) ofthe first embodiment;

FIG. 4 is a schematic sectional view illustrating steps (f) to (g) ofthe first embodiment;

FIG. 5 is a schematic sectional view illustrating steps (h) to (i) ofthe first embodiment;

FIG. 6 is a schematic sectional view illustrating steps (j) to (k) ofthe first embodiment;

FIG. 7 is a schematic sectional view illustrating steps (1) to (n) ofthe first embodiment;

FIG. 8 is a schematic sectional view illustrating steps (a) to (b) of asecond embodiment of a method for producing a power semiconductor devicewith heat dissipating capability according to the present disclosure;

FIG. 9 is a schematic sectional view illustrating steps (c′) to (d′) ofthe second embodiment; and

FIG. 10 is a schematic sectional view illustrating step (e′) of thesecond embodiment.

DETAILED DESCRIPTION

Referring to FIGS. 2 to 6 , a first embodiment of a method for heatdissipation of a power semiconductor device according to the presentdisclosure includes:

-   -   (a) epitaxially growing a GaN-based buffer layer 23 having a        hexagonal crystal structure on a first surface 21 of a sapphire        substrate 2;    -   (b) epitaxially growing a Ga₂O₃ semiconductor layer 3 having a        monoclinic crystal structure on the GaN-based buffer layer 23;    -   (c) forming a source region 31 and a drain region 32 on two        opposite sides of the Ga₂O₃ semiconductor layer 3;    -   (d) forming a source S and a drain D that are respectively        connected to the source region 31 and the drain region 32 of the        Ga₂O₃ semiconductor layer 3;    -   (e) forming a gate dielectric layer 4 covering the Ga₂O₃        semiconductor layer 3, the source S, and the drain D;    -   (f) forming a first gate G1 on the gate dielectric layer 4;    -   (g) forming an insulator layer 5 on the first gate G1;    -   (h) forming a metal adhesive layer 6 on the insulator layer 5;    -   (i) removing part of the metal adhesive layer 6, the insulator        layer 5, and the gate dielectric layer 4 to expose one of the        source S and drain D;    -   (j) conducting an electroforming process to form a heat sink 7        which covers the metal adhesive layer 6, the insulator layer 5,        the gate dielectric layer 4, and the one of the source S and the        drain D; and    -   (k) conducting a laser lift-off process through a second surface        22 of the sapphire substrate 2 opposite to the first surface 21        of the sapphire substrate 2 to remove the sapphire substrate 2        and the GaN-based buffer layer 23, so as to expose surfaces of        the Ga₂O₃ semiconductor layer 3, the source S, and the drain D        that are opposite to the gate dielectric layer 4.

The details of the steps are described below.

In step (a) of this embodiment, the sapphire substrate 2 has a thermalconductivity (κ) of about 40 W/m·K.

In step (a) of this embodiment, the GaN-based buffer layer 23 isepitaxially grown on the first surface 21 of the sapphire substrate 2through metal-organic chemical vapor deposition MOCVD usingtrimethylgallium (TMG, Ga(CH₃)₃) and N₂ as precursors.

In step (b) of this embodiment, the Ga₂O₃ semiconductor layer 3 isepitaxially grown on the GaN-based buffer layer 23 through MOCVD usingTMG and O₂ as precursors.

In step (c) of this embodiment, the source region 31 and the drainregion 32 may be formed by conducting a patterning process to removepart of the Ga₂O₃ semiconductor layer 3 and expose the GaN-based bufferlayer 23. Optionally, after the patterning process, the two oppositesides of the Ga₂O₃ semiconductor layer 3 may be further subjected to anion implantation process to form a high doping concentration.

In step (d) of this embodiment, each of the source S and the drain D isa Ti/Al/Au contact electrode made by sputtering.

In step (e) of this embodiment, the gate dielectric layer 4 is made ofAl₂O₃.

In step (f) of this embodiment, the first gate G1 is a Ni/Au gate madeby sputtering.

In step (g) of this embodiment, the insulator layer 5 is formed on thefirst gate G1 to cover the first gate G1 and the gate dielectric layer4.

In step (i) of this embodiment, after removing the part of the metaladhesive layer 6, the insulator layer 5, and the gate dielectric layer4, the drain D is exposed.

The heat sink 7 may be made of a metal selected from the groupconsisting of silver (Ag), copper (Cu), gold (Au), aluminum (Al), sodium(Na), molybdenum (Mo), tungsten (W), zinc (Zn), nickel (Ni), andcombinations thereof. For instance, the heat sink 7 is made of copper(Cu) having a thermal conductivity (κ) of 401 W/m·K.

In this embodiment, referring to FIG. 7 , the production method mayfurther include:

-   -   (l) forming an oxide layer 8 on the exposed surface of the Ga₂O₃        semiconductor layer 3;    -   (m) forming an electrode pad 9 on the exposed surface of a        respective one of the source S and the drain D; and    -   (n) forming a second gate G2 on the oxide layer 8, the second        gate G2 being configured to be a field plate.

The second gate G2 may be made of Ti/Au to reduce hot electrons and theleakage current effect.

In this embodiment, since the Ga₂O₃ semiconductor layer 3 is epitaxiallygrown, through MOCVD, on the GaN-based buffer layer 23 that is grown onthe first surface 21 of the sapphire substrate 2, the lattice mismatchbetween the GaN-based buffer layer 23 having a hexagonal crystalstructure and the Ga₂O₃ semiconductor layer 3 having a monocliniccrystal structure is low. By virtue of the epitaxial growth process, thethreading dislocation density of the Ga₂O₃ semiconductor layer 3 can bereduced, so that the Ga₂O₃ semiconductor layer 3 has excellent epitaxialquality.

Moreover, the sapphire substrate 2 having a thermal conductivity (κ) ofabout 40 W/m·K is removed by a laser lift-off process, and copper (Cu)having a thermal conductivity (κ) of 401 W/m·K is used to form the heatsink 7 above the Ga₂O₃ semiconductor layer 3, thereby further reducingthe thermal resistance and improving the heat dissipation effect.

In addition, referring to FIGS. 8 to 10 , a second embodiment of theproduction method according to the present disclosure includes:

-   -   (a) epitaxially growing a GaN-based buffer layer 23 having a        hexagonal crystal structure on a first surface 21 of a sapphire        substrate 2;    -   (b) epitaxially growing a Ga₂O₃ semiconductor layer 3 having a        monoclinic crystal structure on the GaN-based buffer layer 23;    -   (c′) forming a metal adhesive layer 6 on the Ga₂O₃ semiconductor        layer 3;    -   (d′) conducting a wafer bonding process to form a heat sink 7 on        the metal adhesive layer 6; and    -   (e′) conducting a laser lift-off process to remove the sapphire        substrate 2 and the GaN-based buffer layer 23, so as to expose a        surface of the Ga₂O₃ semiconductor layer 3 opposite to the metal        adhesive layer.

In the second embodiment, the heat sink 7 may be made of a materialselected from the group consisting of a silicon wafer, a silicon carbidewafer, an aluminum nitride substrate, and combinations thereof.

In the second embodiment, the production method may further include:

-   -   (f′) forming a source region 31 and a drain region 32 on two        opposite sides of the Ga₂O₃ semiconductor layer 3;    -   (g′) forming a source S and a drain D respectively on the source        region 31 and the drain region 32 of the Ga₂O₃ semiconductor        layer 3, so that the source S and the drain D are respectively        connected to the opposite sides of the Ga₂O₃ semiconductor layer        3;    -   (h′) forming a gate dielectric layer 4 covering the exposed        surface of the Ga₂O₃ semiconductor layer 3, the source S, and        the drain D;    -   (i′) forming a first gate G1 on the gate dielectric layer 4; and    -   (j′) forming an insulator layer 5 on the first gate G1.

The formation of the source region 31 and the drain region 32, theformation of the source S and the drain D, and the formation of the gatedielectric layer 4, the first gate G1, and the insulator layer 5 in thesecond embodiment may be similar to those described for the firstembodiment.

In the description above, for the purposes of explanation, numerousspecific details have been set forth in order to provide a thoroughunderstanding of the embodiment(s). It will be apparent, however, to oneskilled in the art, that one or more other embodiments may be practicedwithout some of these specific details. It should also be appreciatedthat reference throughout this specification to “one embodiment,” “anembodiment,” an embodiment with an indication of an ordinal number andso forth means that a particular feature, structure, or characteristicmay be included in the practice of the disclosure. It should be furtherappreciated that in the description, various features are sometimesgrouped together in a single embodiment, figure, or description thereoffor the purpose of streamlining the disclosure and aiding in theunderstanding of various inventive aspects, and that one or morefeatures or specific details from one embodiment may be practicedtogether with one or more features or specific details from anotherembodiment, where appropriate, in the practice of the disclosure.

While the disclosure has been described in connection with what areconsidered the exemplary embodiments, it is understood that thisdisclosure is not limited to the disclosed embodiments but is intendedto cover various arrangements included within the spirit and scope ofthe broadest interpretation so as to encompass all such modificationsand equivalent arrangements.

What is claimed is:
 1. A method for producing a power semiconductordevice with heat dissipating capability, comprising: (a) epitaxiallygrowing a GaN-based buffer layer having a hexagonal crystal structure ona first surface of a sapphire substrate; (b) epitaxially growing a Ga₂O₃semiconductor layer having a monoclinic crystal structure on saidGaN-based buffer layer; (c) forming a source region and a drain regionon two opposite sides of said Ga₂O₃ semiconductor layer; (d) forming asource and a drain that are respectively connected to said source regionand said drain region of said Ga₂O₃ semiconductor layer; (e) forming agate dielectric layer covering said Ga₂O₃ semiconductor layer, saidsource, and said drain; (f) forming a first gate on said gate dielectriclayer; (g) forming an insulator layer on said first gate; (h) forming ametal adhesive layer on said insulator layer; (i) removing part of saidmetal adhesive layer, said insulator layer, and said gate dielectriclayer to expose one of said source and said drain; (j) conducting anelectroforming process to form a heat sink which covers said metaladhesive layer, said insulator layer, said gate dielectric layer, andsaid one of said source and said drain; and (k) conducting a laserlift-off process through a second surface of said sapphire substrateopposite to said first surface of said sapphire substrate to remove saidsapphire substrate and said GaN-based buffer layer, so as to exposesurfaces of said Ga₂O₃ semiconductor layer, said source, and said drainthat are opposite to said gate dielectric layer.
 2. The method accordingto claim 1, wherein in step (j), said heat sink is made of a metalselected from the group consisting of silver, copper, gold, aluminum,sodium, molybdenum, tungsten, zinc, nickel, and combinations thereof. 3.The method according to claim 1, further comprising: (l) forming anoxide layer on said exposed surface of said Ga₂O₃ semiconductor layer;(m) forming an electrode pad on said exposed surface of a respective oneof said source and said drain; and (n) forming a second gate on saidoxide layer, said second gate being configured to be a field plate.
 4. Amethod for producing a power semiconductor device with heat dissipatingcapability, comprising: (a) epitaxially growing a GaN-based buffer layerhaving a hexagonal crystal structure on a first surface of a sapphiresubstrate; (b) epitaxially growing a Ga₂O₃ semiconductor layer having amonoclinic crystal structure on said GaN-based buffer layer; (c′)forming a metal adhesive layer on said Ga₂O₃ semiconductor layer; (d′)conducting a wafer bonding process to form a heat sink on said metaladhesive layer; and (e′) conducting a laser lift-off process through asecond surface of said sapphire substrate opposite to said first surfaceof said sapphire substrate to remove said sapphire substrate and saidGaN-based buffer layer, so as to expose a surface of said Ga₂O₃semiconductor layer opposite to the metal adhesive layer.
 5. The methodaccording to claim 4, wherein in step (d′), said heat sink is made of amaterial selected from the group consisting of a silicon wafer, asilicon carbide wafer, an aluminum nitride substrate, and combinationsthereof.
 6. The method according to claim 4, further comprising: (f′)forming a source region and a drain region on two opposite sides of saidGa₂O₃ semiconductor layer; (g′) forming a source and a drain that arerespectively connected to said source region and said drain region ofsaid Ga₂O₃ semiconductor layer; (h′) forming a gate dielectric layercovering said exposed surface of said Ga₂O₃ semiconductor layer, saidsource, and said drain; (i′) forming a first gate on said gatedielectric layer; and (j′) forming an insulator layer on said firstgate.